Abstract：Chemical mechanical planarization (CMP) process on SiO2 layer is useful for the yield of highly integrated superconducting circuits especially for the ones with stacked Josephson Junction Arrays. Firstly, the CMP process is explored for the planarization on thermal oxide SiO2 and Chemical vapor deposition (CVD) deposited SiO2 layers. The test results show that the polishing rates for the two films above are 2nm/s and 3nm/s, respectively. And the differences in global material removal height within the wafer are both below 20nm. Then it is applied to the fabrication process of Josephson Junction Arrays. The Atomic force microscope (AFM) height profile scan on the junction unit indicates that the Step height (SH) is reduced from 240nm to 25nm and the surface roughness, which is acquired from a 2×2μm2 area on the capping SiO2 isolating layer, is about 0.535nm, and therefore the CMP process on junction arrays patterned wafer provides sufficient process windows for subsequent fabrication processes.
赵欣,曹文会,李劲劲. 用于量子电压基准中约瑟夫森结阵列的CMP平整化工艺研究[J]. 计量学报, 2022, 43(3): 412-415.
ZHAO Xin,CAO Wen-hui,LI Jin-jin. Exploring the CMP Process for Josephson Junction Arrays Used in Voltage Standard. Acta Metrologica Sinica, 2022, 43(3): 412-415.
［1］Thomasson S L, Moopenn A W, Elmadjian R, et al. All refractory NbN integrated circuit process ［J］. IEEE Transactions on Appiled Superconductivity, 1993, 3(1): 2058-2061.
［2］Olaya D, Dresselhaus P D, Benz S P. 300-GHz Operation of Divider Circuits Using High-Jc Nb/NbxSi1-x/Nb Josephson Junctions ［J］. IEEE Transactions on Appiled Superconductivity, 2015, 25 (3): 1-5.
［3］Schulze H, Behr R, Kohlmann J, et al. Design and fabrication of 10 V SINIS Josephson arrays for programmable voltage standards ［J］. Superconductor Science and Technology, 2000, 13(9): 1293-1295.
［4］Numata H, Nagasawa S, Tanaka M, et al. Fabrication Technology for High-Density Josephson Integrated Circuits using Mechanical Polishing Planarization ［J］. IEEE Transactions on Appiled Superconductivity, 1999, 9(2): 3198-3201.
［5］Gurvitch M, Washington M A, Huggins H A. High quality refractory Josephson tunnel junctions utilizing thin aluminum layers ［J］. Applied Physics Letters, 1983, 4(25): 472-474.
［6］Murduck J M, Kirschenbaum A, Mayer A, et al. High-Performance Nb Integrated Circuit Process Fabrication ［J］. IEEE Transactions on Appiled Superconductivity, 2003, 13(2): 87-90.
［7］Meng X, Bhat A, Duzer T Van. Very small critical current spreads in Nb/AlOx/Nb integrated circuits using low temperature and low stress ECR PECVD silicon oxide films［J］. IEEE Transactions on Appiled Superconductivity, 1999, 9(2): 3208-3211.
［8］Thomasson S L, Moopenn A W, Elmadjian R, et al. All refractory NbN integrated circuit process ［J］. IEEE Transactions on Appiled Superconductivity, 1993, 3(1): 2058-2061.
［9］Aoyagi M, Maezawa M, Nakagawa H, et al. Fabrication of submicron Nb/AlOx/Nb Josephson junctions using ECR plasma etching technique ［J］. IEEE Transactions on Appiled Superconductivity, 1997, 7(2): 2644-2648.
［10］Yamamori H, Ishizaki M, Shoji A, et al. 10 V programmable Josephson voltage standard circuits using NbN/TiNx/NbN/TiNx/NbN double-junction stacks ［J］. Applied Physics Letters, 2006, 88(4): 024503.
［11］Rüfenacht A, Howe L A, Fox A E, et al. Cryocooled 10 V Programmable Josephson Voltage Standard ［J］. IEEE Transactions on Instrumentation and Measurement, 2015, 64(6): 1477-1482.
［12］Rüfenacht A, Flowers-Jacobs N E, Benz S P. Impact of the latest generation of Josephson voltage standards in ac and dc electric metrology ［J］. Metrologia, 2018, 55(5): S152-S173.
［13］Bao Z, Bhushan M, Ran S, et al. Fabrication of high quality, deep-submicron Nb/AlOx/Nb Josephson junctions using chemical mechanical polishing ［J］. IEEE Transactions on Appiled Superconductivity, 1995, 5(2): 2731-2734.
［14］Numata H, Nagasawa S, Tanaka M, et al. Fabrication technology for high-density Josephson integrated circuits using mechanical polishing planarization ［J］. IEEE Transactions on Appiled Superconductivity, 1999, 9(2): 3198-3201.
［15］Ishizaki M, Yamamori H, Shoji A, et al. A Programmable Josephson Voltage Standard Chip using Arrays of NbN/TiN/NbN/TiN/NbN Double-Junction Stacks Operated at 10K ［C］//2004 Conference on Precision Electromagnetic Measurements, London, 2004.
［16］Yamamori H, Yamada T, Sasaki H, et al. A 10 V programmable Josephson voltage standard circuit with a maximum output voltage of 20 V ［J］. Superconductor Science and Technology, 2008, 21(10): 105007.
［17］Kieler O F, Iuzzolino R, Kohlmann J. Sub-μm SNS Josephson Junction Arrays for the Josephson Arbitrary Waveform Synthesizer ［J］. IEEE Transactions on Appiled Superconductivity, 2009, 19(3): 230-233.
［18］Cao W H, Li J J, Zhong Y, et al. Study of Nb/NbxSi1-x/Nb Josephson junction arrays ［J］. Chinese Physics B, 2015, 24(12): 127402.
［19］贾正森,王磊,徐熙彤, 等. 基于约瑟夫森量子电压的交流功率测量系统及方法研究［J］. 计量学报, 2020, 41(4): 469-474.
Jia Z S, Wang L, Xu X T, et al. Research on AC Power Measurement System and Method Based on Josephson Quantum Voltage［J］. Acta Metrologica Sinica, 2020, 41(4): 469-474.
［19］郭小玮, 迟宗涛, 曹文会, 等. 约瑟夫森结阵器件的研究进展［J］. 计量学报, 2013, 34(4): 378-382.
Guo X W, Chi Z T, Cao W H, et al. The Research Progress of the Josephson Array Device ［J］. Acta Metrologica Sinica, 2013, 34(4): 378-382.
［20］郑永军, 狄韦宇, 罗哉. 改进遗传算法在CMP终点检测的应用［J］. 计量学报, 2020, 41(10): 1192-1198.
Zheng Y J, Di W Y, Luo Z. Application of Improved Genetic Algorithm in CMP Endpoint Detection ［J］. Acta Metrologica Sinica, 2020, 41(10): 1192-1198.
2022, Vol. 43 
