Abstract：According to the principle of digital phase locked loop (DPLL) based on CORDIC algorithm,the numerically controlled oscillator and loop filter of DPLL are thoroughly researched and designed for the Silicon Micro-machined Gyroscope (SMG) drive mode.On account of the feature that the loop filter parameters of the DPLL have a contradictory impact on the speed and frequency accuracy of the DPLL,a solution is proposed to resolve that conflict,which can change loop filter parameters in the different work period of the DPLL.Detailed simulations of the solution and DPLL based on CORDIC algorithm are done in Simulink and DSPbuilder.Then the hardware of the digital signal processing circuit with the core of FPGA (EP3C16) is designed and debugged.Finally,performance tests of the loop designed are carried out,the results prove that the loop designed could have satisfied the frequency stability need of the SMG drive mode.
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