基于CORDIC算法的PLL在FPGA中的实现

王玉良

doi:10.3969/j.issn.1000-1158.2012.03.15

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计量学报 ›› 2012, Vol. 33 ›› Issue (3) : 259-265. DOI: 10.3969/j.issn.1000-1158.2012.03.15

基于CORDIC算法的PLL在FPGA中的实现

王玉良

作者信息 +

FPGA Implementation of PLL Based on CORDIC Algorithm

WANG Yu-liang

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文章历史 +

摘要

根据硅微陀螺仪驱动模态的特点,利用数字锁相环基本原理,对数字锁相环的压控振荡器和环路滤波器进行了研究与设计。针对环路滤波参数对数字环路锁相速度和稳频精度的影响存在矛盾的特点,提出了一种改变参数的解决方法,并在Simulink和DSPbuilder中对基于CORDIC算法的环路及改变参数的方法进行了详细的仿真验证。最后完成了以EP3C16型号FPGA为核心器件的数字信号处理电路设计与调试,并对设计的环路进行了性能测试,结果表明设计的数字环路可以满足硅微陀螺仪驱动模态的稳频需求。

Abstract

According to the principle of digital phase locked loop (DPLL) based on CORDIC algorithm,the numerically controlled oscillator and loop filter of DPLL are thoroughly researched and designed for the Silicon Micro-machined Gyroscope (SMG) drive mode.On account of the feature that the loop filter parameters of the DPLL have a contradictory impact on the speed and frequency accuracy of the DPLL,a solution is proposed to resolve that conflict,which can change loop filter parameters in the different work period of the DPLL.Detailed simulations of the solution and DPLL based on CORDIC algorithm are done in Simulink and DSPbuilder.Then the hardware of the digital signal processing circuit with the core of FPGA (EP3C16) is designed and debugged.Finally,performance tests of the loop designed are carried out,the results prove that the loop designed could have satisfied the frequency stability need of the SMG drive mode.

导出引用

王玉良. 基于CORDIC算法的PLL在FPGA中的实现[J]. 计量学报. 2012, 33(3): 259-265 https://doi.org/10.3969/j.issn.1000-1158.2012.03.15

WANG Yu-liang. FPGA Implementation of PLL Based on CORDIC Algorithm[J]. Acta Metrologica Sinica. 2012, 33(3): 259-265 https://doi.org/10.3969/j.issn.1000-1158.2012.03.15

中图分类号： TB973

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