Abstract：A presents a parallel processing architecture is described. It can solve some difficult problems of ultra-wideband digital IF processing through multiple channels of parallel processing, which can effectively reduce the sample rate and process cost. The parallel digital down conversion technique principle is deduced, phase difference of multi-NCOs output and error factor for reducing SNR are analyzed, and index distribution basis for the specific engineering design is provided. Finally, its correctness can be verified by experiment.
［1］Walter Tuttlebee. 软件无线电技术与实现［M］.北京:电子工业出版社,2005,1-20.
［2］Petrowski M, Chester D B,Young W R. Single Chip Digital Down Converter Architecture［C］// 1993 IEEE International Conference on Acoustics,Speech,and Signal Processing,Minneapolis, MN, USA , 1993,349-352.
［3］Bai F M, Lv X L, Yan F. Programming design of Digital-Down Converter based on software radio［C］//2010 Second Pacific-Asia Conference on Circuits, Communications and System(PACCS), Beijing, 2010, 351-354.
［4］Hunter M T, Mikhael W B, Kourtellis A G. Wideband Digital Downconverters for Synthetic Instrumentation［J］.IEEE Transactions on Instrumentation and Measurement, 2009, 58(2):263-269.
［5］Yu J Y , Li Y. An efficient digital down converter architecture for wide band radar receiver［C］//2009 IET International Radar conference, Guilin, China, 2009:1-4.
［6］胡广书. 现代信号处理教程［M］. 北京:清华大学出版社,2004,132-141.
［7］田新广,李文法,孙春来,等. 无相位截断情况下DDS的幅度量化杂散特性分析［J］. 仪器仪表学报,2008,29（5）:914-920.
［8］Kidambi S S, El-Guibaly F, Antoniou A. Area-Efficient Multipliers for Digital Signal Processing Applications［J］. IEEE Transactions on circuits and systems II: Analog and Digital Signal Processing, 1996,43（2):90-95.
［9］丁玉美,高西泉. 数字信号处理［M］. 西安:西安电子科技大学出版社,2005,262-264.
2012, Vol. 33 
