Abstract：In the fabrication of quantum voltage chips， thin films of silicon dioxide are used as interlayer dielectric layers （IDL） to realize the electrical connections of Josephson junctions. However， typically silicon dioxide film is conformally deposited and subsequent niobium wire layers are prone to form grain boundary cracks near the rectangular steps. Planarization of the IDL is necessary for lithography and chip reliability considerations. Compared to other planarization schemes， the etch-back method has simple process steps and is suited for research work. A thick photoresist layer is spin-coated over the IDL to fill the trenches in the pattern and form a planar interface. Then， a reactive ion etching system is used to etch back the photoresist and SiO2 at the same speed. A planar dielectric layer surface can be obtained when the photoresist layer is etched up. The same etching rate of photoresist and SiO2 is realized by adjusting the oxygen flow and RF power. Additionally， in order to monitor the planarization status， an end-point detection system is applied in the etch-back process. Based on the light intensity reflected from the substrate surface， one can determine the etching depth and decide when to stop the process. The above method was successfully used to form a planarized dielectric layer above the junction area. By applying this etch-back method in the chip fabrication process， no crack is formed in the niobium wiring layer， and good I-V curves are obtained for the chip. The reliability of the chip is effectively improved.
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2025, Vol. 46 
