量子电压芯片制备中的介质层平坦化

doi:10.3969/j.issn.1000-1158.2025.01.17

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Abstract In the fabrication of quantum voltage chips， thin films of silicon dioxide are used as interlayer dielectric layers （IDL） to realize the electrical connections of Josephson junctions. However， typically silicon dioxide film is conformally deposited and subsequent niobium wire layers are prone to form grain boundary cracks near the rectangular steps. Planarization of the IDL is necessary for lithography and chip reliability considerations. Compared to other planarization schemes， the etch-back method has simple process steps and is suited for research work. A thick photoresist layer is spin-coated over the IDL to fill the trenches in the pattern and form a planar interface. Then， a reactive ion etching system is used to etch back the photoresist and SiO₂ at the same speed. A planar dielectric layer surface can be obtained when the photoresist layer is etched up. The same etching rate of photoresist and SiO₂ is realized by adjusting the oxygen flow and RF power. Additionally， in order to monitor the planarization status， an end-point detection system is applied in the etch-back process. Based on the light intensity reflected from the substrate surface， one can determine the etching depth and decide when to stop the process. The above method was successfully used to form a planarized dielectric layer above the junction area. By applying this etch-back method in the chip fabrication process， no crack is formed in the niobium wiring layer， and good I-V curves are obtained for the chip. The reliability of the chip is effectively improved.

Key words： electrical measurement quantum voltage chip planarization etch back endpoint Josephson junction

Received: 04 March 2024 Published: 14 January 2025

PACS:

TB971

Fund:National Key Research and Development Program of China;National Natural Science Foundation of China

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	Articles by authors
	CAO Yue
	XU Sisi
	ZHONG Yuan
	LI Jinjin
	ZHONG Qing
	CAO Wenhui
	CAI Jinhui

Cite this article:

CAO Yue,XU Sisi,ZHONG Yuan, et al. Interlayer Dielectric Planarization in Quantum Voltage Chip Fabrication[J]. Acta Metrologica Sinica, 2025, 46(1): 106-111.

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http://jlxb.china-csm.org:81/Jwk_jlxb/EN/10.3969/j.issn.1000-1158.2025.01.17 OR http://jlxb.china-csm.org:81/Jwk_jlxb/EN/Y2025/V46/I1/106

3	HAMILTON C A. Josephson voltage standards［J］. Review of scientific instruments， 2000， 71（10）： 3611-3623.
13	ZANTYE P B， KUMAR A， SIKDER A K. Chemical mechanical planarization for microelectronics applications［J］. Materials Science and Engineering： R： Reports， 2004， 45（3-6）： 89-220.
2	SHAPIRO S. Josephson currents in superconducting tunneling： The effect of microwaves and other observations［J］. Physical Review Letters， 1963， 11（2）： 80-82.
12	STEIGERWALD J M， MURARKA S P， GUTMANN R J. Chemical Mechanical Planarization of Microelectronic Materials［M］. New York： John Wiley & Sons， 1997.
8	BENZ S P. Superconductor‐normal‐superconductor junctions for programmable voltage standards［J］. Applied physics letters， 1995， 67（18）： 2714-2716.
18	MELANSON B， SEITZ M， ZHANG J. Investigation of plasma etching for interlayer dielectric planarization in high-efficiency deep-ultraviolet nanowire LEDs ［C］// Advanced Fabrication Technologies for Micro/Nano Optics and Photonics XVI， San Francisco， US， 2023： 104-111.
9	FOX A E， DRESSELHAUS P D， RÜFENACHT A， et al. Junction yield analysis for 10 V programmable Josephson voltage standard devices［J］. IEEE Transactions on Applied Superconductivity， 2015， 25（3）： 1-5.
19	MOUSTAKAS T D， WILLIAMS A D. Planarization of GaN by photoresist technique using an inductively coupled plasma： US Patent 9，230，818［P］. 2016-1-5.
1	JOSEPHSON B D. Possible new effects in superconductive tunnelling［J］. Physics letters， 1962， 1（7）： 251-253.
11	SURYADEVARA B， Advances in Chemical Mechanical Planarization （CMP）［M］. Waltham： Woodhead Publishing， 2016.
21	WANG X， DAI X， WANG H， et al. All-water etching-free electron beam lithography for on-chip nanomaterials［J］. ACS nano， 2023， 17（5）： 4933-4941.
4	RÜFENACHT A， FLOWERS-JACOBS N E， BENZ S P. Impact of the latest generation of Josephson voltage standards in ac and dc electric metrology［J］. Metrologia， 2018， 55（5）： 152-173.
14	NAGASAWA S， HINODE K， SUGITA M， et al. Planarized multi-layer fabrication technology for LTS large-scale SFQ circuits［J］. Superconductor Science and Technology， 2003， 16（12）： 1483-1486.
10	LIANG C， ZHONG Y， ZHONG Q， et al. Low-Temperature Deposition of High-Quality SiO2 Films with a Sloped Sidewall Profile for Vertical Step Coverage［J］. Coatings， 2022， 12（10）： 1411.
20	WILLIAMS A D， MOUSTAKAS T D. Planarization of GaN by the Etch-Back Method［J］. MRS Online Proceedings Library， 2005， 892： 329-334.
5	BAUER S， BEHR R， HERICK J， et al. Josephson voltage standards as toolkit for precision metrological applications at PTB［J］. Measurement Science and Technology， 2022， 34（3）： 032001.
16	KIELER O， WENDISCH R， GERDAU R W， et al. Stacked Josephson junction arrays for the pulse-driven AC Josephson voltage standard［J］. IEEE Transactions on Applied Superconductivity， 2021， 31（5）： 1-5.
6	王振宇，曾九孙，高鹤，等. 远程靶基距Nb/Al-AlOx/Nb约瑟夫森结薄膜溅射制备技术研究［J］. 计量学报， 2023，44（9）： 1333-1338. WANG Z Y， ZENG J S， GAO H， et al. Fabrication of NNb/Al-AlOx/Nb Josephson Junction Films by a Sputtering Process with a Long Target-substrate Distance［J］. Acta Metrologica Sinica， 2023， 44（9）： 1333-1338.
7	YAMADA T， URANO C， NISHINAKA H， et al. Single-chip 10-V programmable Josephson voltage standard system based on a refrigerator and its precision evaluation［J］. IEEE transactions on applied superconductivity， 2009， 20（1）： 21-25.
17	FUJII S， FUKUMOTO M， FUSE G， et al. A planarization technology using a bias-deposited dielectric film and an etch-back process［J］. IEEE transactions on electron devices， 1988， 35（11）： 1829-1833.
15	OLAYA D， CASTELLANOS-BELTRAN M， PULECIO J， et al. Planarized process for single-flux-quantum circuits with self-shunted Nb/NbxSi1-x/Nb Josephson junctions［J］. IEEE Transactions on Applied Superconductivity， 2019， 29（6）： 1-8.