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| Exploring the CMP Process for Josephson Junction Arrays Used in Voltage Standard |
| ZHAO Xin,CAO Wen-hui,LI Jin-jin |
| Center for Advanced Measurement Science, National Institute of Metrology, Beijing 102200, China |
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Abstract Chemical mechanical planarization (CMP) process on SiO2 layer is useful for the yield of highly integrated superconducting circuits especially for the ones with stacked Josephson Junction Arrays. Firstly, the CMP process is explored for the planarization on thermal oxide SiO2 and Chemical vapor deposition (CVD) deposited SiO2 layers. The test results show that the polishing rates for the two films above are 2nm/s and 3nm/s, respectively. And the differences in global material removal height within the wafer are both below 20nm. Then it is applied to the fabrication process of Josephson Junction Arrays. The Atomic force microscope (AFM) height profile scan on the junction unit indicates that the Step height (SH) is reduced from 240nm to 25nm and the surface roughness, which is acquired from a 2×2μm2 area on the capping SiO2 isolating layer, is about 0.535nm, and therefore the CMP process on junction arrays patterned wafer provides sufficient process windows for subsequent fabrication processes.
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Received: 18 November 2020
Published: 23 March 2022
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| Fund:National Key R&D Program of China |
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2022, Vol. 43 
