Acta Metrologica Sinica  2023, Vol. 44 Issue (11): 1735-1739    DOI: 10.3969/j.issn.1000-1158.2023.11.15
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Traceability and Measurement Method for On-wafer Capacitance Test System
DING Chen,QIAO Yu-e,LIU Yan,ZHAI Yu-wei,WU Ai-hua
The 13th Research Institute of China Electronics Technology Group Corporation, Shijiazhuang, Hebei 050051,China
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Abstract  A traceability and measurement method was proposed in order to solve the problem that the capacitance parameter of on-wafer traceability and inaccurate measurement. The measurement results were connected with the four-terminal par capacitor standard by the on chip straight line to realize the traceability. Adopting the quantitative research of interference loop, corrected the influence of the probe system and cable, and accurated measurement of on wafer capacitance. The measurement accuracy of the metering levels test system improved 0.08% by this method.
Key wordsmetrology      on-wafer capacitance      on chip straight line      four-terminal par capacitor      interference loop      traceability     
Received: 14 June 2022      Published: 17 November 2023
PACS:  TB973  
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DING Chen
QIAO Yu-e
LIU Yan
ZHAI Yu-wei
WU Ai-hua
Cite this article:   
DING Chen,QIAO Yu-e,LIU Yan, et al. Traceability and Measurement Method for On-wafer Capacitance Test System[J]. Acta Metrologica Sinica, 2023, 44(11): 1735-1739.
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http://jlxb.china-csm.org:81/Jwk_jlxb/EN/10.3969/j.issn.1000-1158.2023.11.15     OR     http://jlxb.china-csm.org:81/Jwk_jlxb/EN/Y2023/V44/I11/1735
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