Improvement of high-speed optical scanner performance based on reuse model
LUO Ying1,ZHANG Tong1,2,LIU Lin1,SONG Yun-cen1,YE Yu-tang1,LIU Yong1
1.Lab of MOEMIL, University of Electronic Science and Technology of China, Chengdu, Sichuan 610054, China
2.Chengdu HOLDTECS Co. Ltd., Chengdu, Sichuan 610054, China
Abstract:A JPEG image compression method based on FPGA and DDR II is proposed. The A3 high-speed scanner is designed and realized. The issue of mutual restraint between the hardware resource and the scanning speed in the high-speed scanner is solved. Basic principle is to build flexible, fast large amount of data storage and transmission mode while reducing the consumption of on-chip RAM through the internal and external storage type water reuse model. And using an efficient time-multiplexed data link to implement the JPEG image compression further improves the compression and transmission speed of hardware module. Theoretical analysis and experimental results show that using the A3 high-speed scanner designed with low-end FPGA chip, the speed of scanning A3 wide paper under a 300dpi resolution can reach 140 page per minute, scanning time delay is less than 1ms, peak signal noise ratio as high as 86.9dB before and after compression, and this fully meets the requirements of high-end high-speed scanners. The high-speed scanners for hardware resource requirements are greatly reduced under the implementation of the model, and this model can also be promoted to apply in other high-speed scanner with different format.
[1]Okuda Y,Yamashita K,Fujieda I.Spectral imaging with a modified document scanner[C]//2010 International Symposium on Optomechatronic Technologies, ISOT 2010, Toronto, ON, Canada, 2010.
[2]喻洋.基于光学宽幅高速扫描仪的网上阅卷系统软件设计[D].成都:电子科技大学, 2012.
[3]Nishikawa Y,Kawahito, Furuta M,et al.A high-speed CMOS image sensor with on-chip parallel image compression circuits[C]//2007 IEEE Custom Integrated Circuits Conference, CICC, San Jose, CA, US, 2008.
[4]Watanabe Y, Itoyama K, Yamada Mro, et al. Digitization of deformed documents using a high-speed multi-camera array[C]//11th Asian Conference on Computer Vision, ACCV 2012, Daejeon, Korea, 2013.
[5]Thierschmann M, Barthel K U,Martin U E. A scalable DSP-architecture for high-speed color document compression[C]// Document Recognition and Retrieval VIII, San Jose, CA, US, 2001.
[6]Sanjeevannanavar S, Nagamani A N. Efficient design and FPGA implementation of JPEG encoder using verilog HDL[C]// International Conference on Nanoscience, Engineering and Technology, ICONSET 2011, Chennai, India, 2011.
[7]Kusuma E D,Widodo T S.FPGA implementation of pipelined 2D-DCT and quantization architecture for JPEG image compression[C]//2010 International Symposium on Information Technology, ITSim’10, Kuala Lumpur, Malaysia, 2010.
[8]Liu R,Lui P L,Zhao H X.Design and implementation of high-speed JPEG image encoding system based on FPGA[C]// 2nd International Conference on Multimedia Technology, ICMT 2011, Hangzhou, China, 2011.
[9]陈普跃,赵新璧,陈斌.二维DCT快速算法及FPGA实现[J].电子质量, 2008,(2):5-7/22.
[10]Megalingam R K,Vineeth S V,Venkat K B, et al.Novel low power, high speed hardware implementation of 1D DCT/IDCT using Xilinx FPGA[C]//2009 International Conference on Computer Technology and Development, ICCTD 2009, Kota Kinabalu, Malaysia, 2009.