Abstract:Aiming at the problem of channel mismatch calibration in time-interleaved ADCs (TIADC), the characteristics of channel mismatch phenomena are firstly analyzed, then system calibration model is built based on reference channel, finally a new calibration approach called multi-frequency reference error method is introduced. This method can efficiently complete effective error compensation by fast frequency calculation and look up table. In addition to that, the applicability and calibration performance of the method in the whole input bandwidth of TIADC are further discussed. The simulation demonstrated that multi-frequency reference error method can improve the SFDR of TIADC beyond 25 dB.
[1]Poulton K, Neff R, Setterberg B, et al. A 20GS/s 8 b ADC with a 1MB memory in 0.18 μm CMOS[C]// IEEE and University of Pennsylvania.IEEE International Solid-State Circuits Conference, San Francisco, USA, 2003, 318-496.
[2]Khoini-poorfard R,Johns D A.Time-interleaved oversampling converters[J]. Electronic Letters, 1993, 29(19): 1673-1674.
[3]朱肇轩,王厚军,王志刚. 并行采样时多带信号重构函数的一种确定方法[J]. 计量学报, 2009, 30(6):559-562.
[4]Yotsuyanagi M, Etoh T,Hirata K.A 10-b 50-MHz pipelined CMOS A/D converter with S/H[J]. IEEE Journal of Solid-State Circuits,1993,28(3):292-300.
[5]Conroy C S G, Clines D W, Gray P R. An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS[J].IEEE Journal of Solid-State Circuits, 1993, 28(4):447-454.
[6]Nakamura K, Hotta M,Carley L R, et al.An 85mW, 10b, 40Msample/s CMOS parallel-pipelined ADC[J]. IEEE Journal of Solid-State Circuits, 1993, 30(3): 173-183.
[7]Kim K Y, Kusayanagi N,Abidi A A. A 13-b 10-MS/s CMOS A/D converter[J]. IEEE Journal of Solid-State Circuits, 1997, 32(3):302-311.
[8]Dyer K, Fu D, Hurst P, et al. A comparison of monolithic background calibration in two time-interleaved analog-to-digital converters[C]// ICASSP. 1998 IEEE Internatinal Symposium on Proceedings of Circuits and Systems,Seattle, Washington, USA, 1998,13-16.
[9]Kim K Y, Kusayanagi N, Abidi A A.A 10-b, 100-MS/s CMOS A/D converter[J]. IEEE Journal of Solid-State Circuits, 1997, 32(3):302-311.
[10]Jin H,Lee E K F. A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs.[J]. IEEE Trans On Circuits, System II, 2000, 47(7): 603-613.
[11]Vogel C. The impact of combined channel mismatch effects in time-interleaved ADCs[J]. IEEE Trans On Instrumentation and Measurement, 2005, 54(1): 415-427.