Abstract：In the fabrication of quantum voltage chips, thin films of silicon dioxide are used as interlayer dielectric layers (IDLs) to realize the electrical connections of Josephson junctions. However, typically the silicon dioxide is conformally deposited and subsequent niobium wire layers are prone to form grain boundary cracks near rectangular steps. Planarization of the IDL is necessary for lithography and reliability reasons. Compared to other planarization schemes, the sacrificial layer back etching method has simple process steps and is well suited for small-volume research work. The IDL is spin-coated to cover a thick photoresist layer to fill the trenches in the pattern and form a planar interface, and then the photoresist and SiO2 are removed at equal speeds using reactive ion beam etching, and a planar dielectric layer surface can be obtained by completely etching to the SiO2 layer as a whole, thus eliminating the insulating layer steps. The isochronous etching of photoresist and SiO2 is realized by adjusting the oxygen flow and RF power. In addition, in order to monitor the planarization status in real time, an end-point detection system is applied to the back-etching process. Based on the reflected light intensity variation curve tracked by the system to determine the etching depth and decide when to stop the process. The above method was successfully used to form a dielectric layer with appropriate thickness, planar surface and lower roughness above the junction area. Applying the sacrificial layer back-etching method to the preparation of the chip, a niobium line layer without cracks and a good DC characteristic curve were obtained, proving that the new process effectively improves the reliability of the chip.
2025, Vol. 46 
